Three-dimensional vertical NAND strings having one bit per cell are disclosed in an article by T. Endoh, et. al., titled “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proc. (2001) 33-36. In a conventional process flow, a 2-film semiconductor channel is formed. The first semiconductor channel layer typically includes a “cover” amorphous silicon layer that covers a tunneling dielectric layer during an anisotropic etch that physically exposes an underlying semiconductor material at the bottom of a memory opening, and the second semiconductor channel layer includes a “body” amorphous silicon layer. The total thickness of the semiconductor channel is typically in a range from 15 nm to 20 nm.
One issue with a semiconductor channel employing two layers of amorphous silicon is that a defective interface is formed between a first polysilicon layer derived from the cover amorphous silicon layer and a second polysilicon layer derived from the body amorphous silicon layer. Such a defective interface leads to degradation of charge carrier mobility and cell current. The defects at the interface between two polysilicon films and defects at grain boundaries, typical for polysilicon, are detrimental to various device performance parameters such as cell current, sub-threshold slope and boosting potential.
In addition, re-sputtered etch ions damage the cover amorphous silicon layer during the anisotropic etch that forms an opening through the cover amorphous silicon layer. Since the cover amorphous silicon layer is converted into a portion of the semiconductor channel, the plasma damage remains within the semiconductor channel. Thus, the quality of the semiconductor channel, as measured by performance, variability and reliability, is degraded.